View LT8610_4607717.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3504 1 3504f typical a pplica t ion fea t ures a pplica t ions descrip t ion quad 40v/1a step-down switching regulator with 100% duty cycle operation the lt ? 3504 consists of four 1a output current buck regulators. the lt3504 has a wide operating input range of 3.2v to 40v. an on-chip boost regulator allows each channel to operate up to 100% duty cycle and eliminates the need for four external charge pump circuits. the lt3504 is designed to minimize external component count and results in a simple and small application circuit. the lt3504 operates robustly in fault conditions. cycle- by-cycle peak current limit and catch diode current limit sensing protect the part during overload conditions. ther - mal shutdown protects the power switches at elevated temperatures. soft-start helps keep the peak inductor current under control during startup. the lt3504 also features output voltage tracking and sequencing, programmable frequency, programmable undervoltage lockout, and a power good pin to indicate when all outputs are in regulation. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. quad buck regulator in 4 5 qfn n wide input range: 3.2v to 40v n four 1a outputs n 100% duty cycle operation n resistor-programmed constant frequency n short-circuit robust n wide sync range: 250khz to 2.2mhz n anti-phase switching reduces ripple n 800mv fb voltage n independent run/soft-start pins n shutdown with uvlo n internal compensation n thermal shutdown n tiny 28-lead (4mm 5mm) thermally enhanced qfn package n automotive battery regulation n industrial control supplies n wall transformer regulation n distributed supply regulation lt3504 start-up and shutdown waveform. v in (top trace) is ramped from 0v up to 8v and then back down to 0v. the other four traces are the output voltages of all four channels 3504 ta01a sw4 da4 fb4 sw3 da3 fb3 sw2 da2 fb2 sw1 da1 fb1 sky sw5 en/uvlo v in v in v in v in run/ss1 run/ss2 run/ss3 run/ss4 rt/sync 5v/1a 10h 52.3k 10k 10f 3.3v/1a 6.8h 10h 31.6k 10k 10f 1f v in 5.4v to 20v transient to 40v 50nf 1 f 1 f 2.5v/1a 4.7h 22.1k 10k 22f 1.8v/1a 3.3h 24.9k 20k 18.2k f sw = 1mhz 22f gnd lt3504 100ms/div 3504 ta01b 5v channel begins 100% dc operation uvlo = ~2.9v parts shuts off 3.3v channel begins 100% dc operation v in 1v/div ch4 1v/div ch3 1v/div ch2 1v/div ch1 1v/div
lt3504 2 3504f p in c on f igura t ion a bsolu t e maxi m u m r a t ings en/uvlo pin ............................................................. 40v e n/uvlo pin above v in pin ........................................ 5v v in pin ...................................................................... 4 0v sky pin ..................................................................... 4 6v sw5 pin .................................................................... 47 v run/ss pins ............................................................... 6v f b pins ........................................................................ 6v rt /sync pin ............................................................... 6v p g pin ....................................................................... 25 v operating junction temperature range (notes 2, 8) lt3504eufd .......................................... C 40c to 125c lt3504iufd ........................................... C 40c to 125c storage temperature range .................. C 65c to 150c (note 1) 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 29 gnd 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 da2 sw2 da3 sw3 sw1 da1 sw4 da4 fb2 fb3 fb1 fb4 gnd rt/sync en/uvlo run/ss3 v in gnd v in sky sw5 pg v in gnd v in run/ss4 run/ss1 run/ss2 7 17 18 19 20 21 22 16 8 15 ja = 43c/w exposed pad (pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range lt3504eufd#pbf lt3504eufd#trpbf 3504 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3504iufd#pbf lt3504iufd#trpbf 3504 28-lead (4mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elec t rical charac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v unless otherwise noted. symbol conditions min typ max units en/uvlo threshold voltage rising l 1.2 1.44 1.6 v en/uvlo threshold voltage hysteresis 110 mv en/uvlo threshold current hysteresis v en/uvlo = measured rising threshold C 50mv (note 3) 1.3 a internal v in undervoltage lockout 2.4 2.9 3.2 v quiescent current (v in ) in shutdown v en/uvlo = 0v 0.01 2 a quiescent current (v in ) v en/uvlo = 1v (note 4) 4 10 a quiescent current (v in ) v en/uvlo = 1.5v, v run/ss(1,2,3,4) = open, v fb(1,2,3,4) = 0.9v, v sky = 17v 2.7 ma quiescent current (sky) v en/uvlo = 1.5v, v run/ss(1,2,3,4) = open, v fb(1,2,3,4) = 0.9v, v sky = 17v 4.4 ma
lt3504 3 3504f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3504euf is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3504iuf is guaranteed over the full C40c to 125c operating junction temperature range. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v unless otherwise noted. note 3: current flows into pin. note 4: quiescent current (v in ) is measured at v en/uvlo = 1v note 5: current flows out of pin. note 6: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. symbol conditions min typ max units run/ss pin source current v run/ss = 0v 1.3 a run/ss pin threshold for switching v fb = 0v 50 100 mv feedback voltage l 790 784 800 800 810 816 mv mv fb pin current v fb = measured v fb (note 5) l 15 150 na reference line regulation v in = 5v to 40v C0.015 %/v sky pin current i sw = 1a 27 40 ma sky voltage above v in voltage v sky C v in 4.85 v switching frequency r t = 6.34k r t = 18.2k r t = 100k l l l 1.8 0.85 200 2.1 1 250 2.4 1.15 300 mhz mhz khz switching phase r t = 18.2k 150 180 210 deg sync threshold voltage 0.9 1.6 v sync input frequency 0.25 2.2 mhz switch current limit (sw1,2,3,4) (note 6) 1.45 1.75 2.1 a switch v cesat (sw1,2,3,4) i sw = 1a 400 mv switch leakage current (sw1,2,3,4) 0.1 2 a catch diode current limit (sw1,2,3,4) fb = 0v fb = 0.7v 0.92 1.15 1.15 1.45 1.33 1.67 a a switch current limit (sw5) (note 6) 220 320 ma switch v cesat (sw5) i sw = 200ma 230 mv switch leakage current (sw5) 0.1 2 a boost diode current limit (sw5) v in = 5v 350 450 ma pg threshold offset v fb rising 65 90 125 mv pg hysteresis v fb rising C v fb falling 35 mv pg voltage output low i pg = 250a 180 300 mv pg pin leakage v pg = 2v 0.01 1 a
lt3504 4 3504f typical p er f or m ance c harac t eris t ics efficiency, f = 1mhz efficiency, f = 1mhz efficiency, f = 1mhz efficiency, f = 1mhz load regulation en/uvlo threshold en/uvlo pin current t a = 25c, unless otherwise noted. load current (a) 0 efficiency (%) 40 60 1 3504 g01 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v v out = 1.8v load current (a) 0 efficiency (%) 40 60 1 3504 g02 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 90 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v v out = 2.5v load current (a) 0 efficiency (%) 40 60 1 3504 g03 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 90 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v v out = 3.3v load current (a) 0 efficiency (%) 40 60 1 3504 g04 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 100 90 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v v out = 5v load current (a) 0 percent error (%) ?3.0 ?2.0 1 3504 g05 ?4.0 ?5.0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 0 ?0.5 ?1.0 ?3.5 ?2.5 ?4.5 ?1.5 v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v v in = 12v efficiency 5v/3.3v/2.5v/1.8v, f = 1mhz efficiency, f = 1mhz load current each channel (a) 0 overall application efficiency (%) 40 60 1 3504 g06 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 100 90 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v v out1,2,3,4 = 5v load current each channel (a) 0 overall application efficiency (%) 40 60 1 3504 g07 20 0 0.2 0.1 0.3 0.5 0.4 0.6 0.7 0.9 0.8 100 90 80 30 50 10 70 v in = 6v v in = 12v v in = 24v v in = 36v temperature (c) ?50 threshold (v) 1.30 1.40 125 3504 g08 1.20 0 ?25 25 75 50 100 1.60 1.55 1.50 1.25 1.35 1.45 falling rising v en/uvlo (v) 0 i en/uvlo (a) 0.8 1.2 2.0 3504 g09 0 0.4 0.2 0.6 1.0 0.8 1.2 1.6 1.4 1.8 2.0 1.8 1.6 0.4 0.6 0.2 1.0 1.4 25c ?45c 150c
lt3504 5 3504f input voltage undervoltage lockout v in pin current typical p er f or m ance c harac t eris t ics run/ss vs fb voltage soft start current switching frequency vs temperature switch voltage drop switch voltage drop, i sw = 500ma switch and diode current limit switch current limit t a = 25c, unless otherwise noted. temperature (c) ?50 uvlo (v) 2.2 2.8 125 3504 g10 2.0 0 ?25 25 75 50 100 3.6 3.4 3.2 2.4 2.6 3.0 v en/uvlo (v) 0 i vin (a) 4 6 2.0 3504 g11 0 0.4 0.2 0.6 1.0 0.8 1.2 1.6 1.4 1.8 10 9 8 2 3 1 5 7 run/ss voltage (mv) 0 fb voltage (mv) 400 1200 3504 g12 0 400 200 600 1000 800 900 800 700 200 300 100 500 600 temperature (c) ?50 i run/ss (a) ?1.8 ?1.2 125 3504 g13 ?2.0 0 ?25 25 75 50 100 0 ?0.6 ?0.8 ?0.2 ?0.4 ?1.6 ?1.4 ?1.0 temperature (c) ?50 frequency (mhz) 0.90 150 3504 g14 0.80 50 250?25 75 125 100 1.20 1.10 1.15 1.05 0.85 0.95 1.00 switch current (ma) 0 switch voltage drop (mv) 100 1000 3504 g15 0 200 400 800 600 600 500 400 200 300 temperature (c) ?50 switch voltage drop (mv) 240 125 3504 g16 200 0 ?25 25 75 50 100 320 300 280 220 260 temperature (c) ?50 current limit (a) 1.2 125 3504 g17 1.0 0 ?25 25 75 50 100 2.0 1.9 1.4 1.1 1.3 1.5 1.7 1.8 1.6 duty cycle (%) 0 switch current limit (a) 1.1 100 3504 g18 1.0 20 40 80 60 2.0 1.9 1.4 1.2 1.3 1.5 1.8 1.6 1.7
lt3504 6 3504f typical p er f or m ance c harac t eris t ics feedback voltage power good threshold operating waveforms, discontinuous mode operating waveforms, continuous mode switch beta minimum on-time temperature (c) ?50 beta 50 125 3504 g19 40 0 ?25 25 75 50 100 70 60 45 55 65 0.5a 1a temperature (c) ?50 on-time (ns) 70 125 3504 g20 50 0 ?25 25 75 50 100 120 90 60 80 100 110 temperature (c) ?50 feedback voltage (mv) 797 125 3504 g21 795 0 ?25 25 75 50 100 805 799 796 798 800 801 802 803 804 temperature (c) ?50 threshold (mv) 640 125 3504 g22 600 0 ?25 25 75 50 100 740 680 620 660 700 720 falling rising 500ns/div 3504 g23 sw1 10v/div sw2 10v/div sw3 10v/div sw4 10v/div i out1,2,3,4 = 40ma v out1,2,3,4 = 5v 500ns/div 3504 g24 sw1 10v/div sw2 10v/div sw3 10v/div sw4 10v/div i out1,2,3,4 = 0.5a v out1,2,3,4 = 5v
lt3504 7 3504f p in func t ions da (pins 1, 3, 6, 8): return the schottky catch diode anode to the diode anode (da) pin. an internal compara - tor senses the diode current and prevents switching when the diode current is higher than the da pin current limit. sw (pins 2, 4, 5, 7): the sw pins are the output of the internal power switches. connect each sw pin to an in- ductor and schottky catch diode cathode. v in (pins 9, 11, 26, 28): the v in pins supply current to the lt3504s internal regulator and to the internal power switches. the v in pins should be tied together and locally bypassed with a capacitor to ground, preferably to pins 10 and 27. gnd (pins 10, 18, 27, exposed pad pin 29): tie the gnd pins to a local ground plane below the lt3504 and the circuit components. the exposed pad must be soldered to the pcb and electrically connected to ground. use a large ground plane and thermal vias to optimize thermal performance. run/ss (pins 12, 13, 14, 15): the run/ss pins are used to soft start each channel and to allow each channel to track other outputs. output tracking is implemented by connecting a resistor divider to this pin from the tracked output. for soft start, tie a capacitor from this pin to ground. an internal 1.3a soft-start current charges the capacitor to create a voltage ramp at the pin. each channel can be individually shut down by pulling run/ss below 0.1v. en/uvlo (pin 16): the en/uvlo pin is used to start up the internal regulator to power the reference and oscilla - tor. it also starts up the internal boost regulator. pull the en/uvlo pin below 1.44v to shut down the lt3504. the lt3504 will draw less than 10a of current from the v in pin when en/uvlo is less than 1.44v. pull en/uvlo pin below 0.7v to put the lt3504 in a state where the part draws 0a from the v in pin. the threshold can function as an accurate undervoltage lockout (uvlo), preventing the regulator from operating until the input voltage has reached the programmed level. do not drive the en/uvlo pin more than 5v above v in . rt/sync (pin 17): set the switching frequency of the lt3504 by tying an external resistor from this pin to ground. select the value of the programming resistor (r t ) according to table 1 in the applications information section. the rt/sync pin is also used to synchronize the internal oscillator of the lt3504 to an external signal. the synchronization (sync) signal is directly logical compatible and can be driven by any signal with pulse width greater than 50ns. the synchronization range is from 250khz to 2.2mhz. fb (pins 19, 20, 21, 22): each feedback pin is regulated to 800mv. connect the feedback resistor divider to this pin. the output voltage is programmed according to the following equation: r1 = r2 ? v out 0.8v ? 1 ? ? ? ? ? ? where r1 connects between out and fb, and r2 connects between fb and gnd. a good value for r2 is 10k?. pg (pin 23): the power good pin is the open collector output of an internal comparator. pg remains low until all fb pins are greater than 710mv. if not in use, this pin can be left unconnected. the pg comparator is disabled in shutdown. sw5 (pin 24): the sw5 pin is an open collector of an internal boost regulator power switch. this power switch generates the drive voltage 4.85v above the input voltage (v in ), to drive the internal buck regulator power switches. connect an inductor from this pin to the v in pin. sky (pin 25): the sky pin is the output of an integrated power schottky diode and is the source of drive voltage to the internal buck regulator power switches. connect a 1f capacitor from this pin to the v in pin. do not drive this pin with an external voltage source. do not draw current from this pin with an external component.
lt3504 8 3504f b lock diagra m 3504 bd v in s r nq s r nq sync detect clk1 clk2 osc frequency to current to ch2, ch4 startup/shutdown thermal shutdown 0.4v 1.3a 1.44v on ref precision uvlo v in en/uvlo lock 1shot slope slope 1shot to ch3 sky 4.85v boost error amp 0.7v boost switch and drive sw5 sw1 da1 pg sky v in pgood out1 comparators from other channels fb1 0.72v current limit foldback 0.8v 0.7v skybad 0.8v boost regulator q5 d5 q1 switch and drive one of the four buck regulators shown power good logic rt/sync run/ss1 fb1 gnd 2.2v 0.1v 4.5v ramp 1a skybad sky v in skybad 0 1 + ?
lt3504 9 3504f o pera t ion a comparator starts the reference when the en/uvlo pin rises above the 1.44v rising threshold. other comparators prevent switching when the input voltage is below 2.9v or the die temperature is above 175c. when the en/uvlo is above 1.44v, the input voltage is above 3.2v, and the temperature is below 175c, the boost regulator begins switching and charges the sky capacitor to 5v above v in . when the sky voltage is less than 4.5v above v in , the run/ss pins and v c nodes are actively pulled low to prevent the buck regulators from switching. the boost regulator (channel 5) consists of an internal 0.4a power switch (q5), an internal power schottky diode (d5), and the necessary logic and other control circuitry to drive the switch. the switch current is monitored to enforce cycle-by-cycle current limit. the diode current is monitored to prevent inductor current runaway during transient conditions. an error amplifier servos the sky voltage to 4.85v above v in . a comparator detects when the sky voltage is 4.5v above v in and allows the buck regulators to begin switching. the oscillator produces two antiphase clock signals running at 50% duty cycle. channels 1, 3 and 5 run antiphase to channels 2 and 4. the oscillator can be programmed by connecting a single resistor from rt/sync to ground, or by applying an external clock signal to rt/sync. a sync detect circuit distinguishes between the type of input. tying a resistor to gnd directly sets the bias current of the oscillator. the sync signal is converted to a current to set the bias current of the oscillator. the oscillator enables an r s flip-flop, turning on the internal 1.7a power switch q1. an amplifier and compara- tor monitor the current flowing between the v in and sw pins, turning the switch off when this current reaches a level determined by the voltage at the v c node. a second comparator enforces a catch diode current limit to prevent inductor current runaway during transient conditions. an error amplifier measures the output voltage through an external resistor tied to the fb pin and servos the v c node. if the error amplifiers output increases, more current is delivered to the output; if it decreases, less current is delivered. a clamp on the v c pin provides switch current limit. each buck regulator switch driver operates by drawing current from the sky pin. regulating the sky pin to 4.85v above the v in pin voltage is necessary to fully saturate the bipolar power switch for efficient operation. soft-start is implemented by generating a voltage ramp at the run/ss pin. an internal 1.3a current source pulls the run/ss pin up to 2.1v. connecting a capacitor from the run/ss pin to ground programs the rate of the voltage ramp on the run/ss pin. a voltage follower circuit with a 0.1v offset connected from the run/ss pin to the ramp node prevents switching until the voltage at the run/ss pin increases above 0.1v. when the voltage at the ramp node is less than 0.9v, the error amplifier servos the fb voltage to the ramp node voltage. when the ramp node voltage increases above 0.9v, then the error amplifier ser - vos the fb voltage to 0.8v. additionally, a current amplifier reduces the catch diode current limit when the fb voltage is below 0.8v to limit the inductor current during startup. each individual buck regulator can be placed in shutdown by pulling the respective run/ss pin below 0.1v. the en/ uvlo pin can be pulled low (below a v be ) to place the entire part in shutdown, disconnecting the outputs and reducing the input current to less than 2a.
lt3504 10 3504f fb resistor network the output voltage is programmed with a resistor divider connected from the output and the fb pin. choose the 1% resistor according to: r1 = r2 ? v out 0.8v ? 1 ? ? ? ? ? ? a good value for r2 is 10k, r2 should not exceed 20k to avoid bias current error. input voltage range the input voltage range for lt3504 applications depends on the output voltage and on the absolute maximum rat- ing of the v in pin. the minimum input voltage to regulate the output gener - ally has to be at least 400mv greater than the greatest programmed output voltage. the only exception is when the largest programmed output voltage is less than 2.8v. in this case the minimum input voltage is 3.2v. the absolute maximum input voltage of the lt3504 is 40v and the part will regulate output voltages as long as the input voltage remains less than or equal to 40v. however for constant-frequency operation (no pulse- skipping) the maximum input voltage is determined by the minimum on-time of the lt3504 and the programmed switching frequency. the minimum on-time is the shortest period of time that it takes the switch to turn on and off. a pplica t ions i n f or m a t ion therefore the maximum input voltage to operate without pulse skipping is: v in(ps) = [ (v out + v d )/(f sw ? t on(min) ) ] + v sw C v d where: ? v in(ps) is the maximum input voltage to operate in constant frequency operation without skipping pulses. ? v out is the programmed output voltage ? v sw is the switch voltage drop, at i out = 1a, v sw = 0.4v ? v d is the catch diode forward voltage drop, for an ap - propriately sized diode, v d = 0.4v ? f sw is the programmed switching frequency ? t on(min) is the minimum on-time, worst-case over temperature = 110ns (at t = 125c) at input voltages that exceed v in(ps) the part will continue to regulate the output voltage up to 40v. however the part will skip pulses (see figure 1) resulting in unwanted harmonics, increased output voltage ripple, and increased peak inductor current. provided that the inductor does not saturate and that the switch current remains below 2a, operation above v in(ps) is safe and will not damage the part. for a more detailed discussion on minimum on-time and pulse-skipping, refer to the applications information section of the lt3505 data sheet. figure 1a: the lt3504 operating in constant-frequency operation (below v in(ps) ), v in = 26.5v, v out = 3.3v, f sw = 2mhz, t on(min) = 74ns at t = 25c figure 1b.the lt3504 operating in pulse-skipping mode (above v in(ps) ), v in = 27v, v out = 3.3v, f sw = 2mhz, t on(min) = 74ns at t = 25c 2s/div 3504 f01a i l 0.5a/div v sw 10v/div 2s/div 3504 f01b i l 0.5a/div v sw 10v/div
lt3504 11 3504f applica t ions in f or m a t ion frequency selection the maximum frequency that the lt3504 can be pro - grammed to is 2.5mhz. the minimum frequency is 250khz. the switching frequency can be programmed in two ways. the first method is by tying a 1% resistor (r t ) from the rt/sync pin to ground. table 1 can be used to select the value of r t . the second method is to synchronize (sync) the internal oscillator to an external clock. the external clock must have a minimum amplitude from 0v to 1.5v and a minimum pulse-width of 50ns. table 1. rt/sync pin resistance to program oscillator frequency frequency (mhz) rt/sync pin resistance (k) 0.20 140 0.3 82.5 0.4 56.2 0.5 43.2 0.6 34.8 0.7 28.0 0.8 23.7 0.9 20.5 1.0 18.2 1.1 16.9 1.2 14.7 1.3 13.0 1.4 11.5 1.5 10.7 1.6 9.76 1.7 8.66 1.8 8.06 1.9 7.32 2.0 6.81 2.1 6.34 2.2 6.04 2.3 5.62 2.4 5.36 2.5 4.99 in certain applications, the lt3504 may be required to be alive and switching for a period of time before it begins to receive a sync signal. if the sync signal is in a high impedance state when it is inactive then the solution is to figure 2. driving the rt/sync pin from a port that is in a high impedance state when it is inactive figure 3. driving the rt/sync pin from a port that is in a low impedance state when it is inactive simply tie an r t resistor from the rt/sync pin to ground (figure 2). the sync signal should be capable of driving the r t resistor. if the sync signal is in a low impedance state or an unknown state when it is inactive, then the solution is to tie the r t resistor from the rt/sync pin to ground and then to drive the rt/sync pin with the sync signal through a 1nf capacitor as shown in figure 3. 3504 f02 port gnd lt3504 rt/sync r t 3504 f03 port 1nf gnd lt3504 rt/sync r t boost regulator and sky pin considerations the on-chip boost regulator generates the sky voltage to be 4.85v above v in . the sky voltage is the source of drive current for the buck regulators which is used to fully saturate the power switch. the boost regulator requires two external components: an inductor and a capacitor. a good first choice for an inductor is given by: l = 20.5h f where f is in mhz. thus, for a 250khz programmed switching frequency, a good first choice for an inductor value is 82h. for a 2.5mhz programmed switching frequency, a good first
lt3504 12 3504f a pplica t ions i n f or m a t ion choice for an inductor value is 8.2h. these values will ensure that each buck regulator will have sufficient drive current to saturate the power switch in all applications and under all operating conditions. a user desiring a lower inductor current value can calculate their optimum inductor size based on their output cur - rent requirements. each buck regulator instantaneously requires 20ma from the sky pin per 1a of switch current. the average current that each buck regulator draws from the sky pin is 20ma multiplied by the duty cycle. so if all four buck regulators run at 100% duty cycle with each channel supplying 1a of output current, then the sky pin should be able to source 80ma. however if each chan - nel runs at 50% duty cycle then the sky pin only has to source 40ma. alternatively if each channel runs at 100% duty cycle but the output current requirement is 0.5a per channel instead of 1a, then again the sky pin only has to source 40ma. to summarize, the sky pin output current requirement is calculated from the following equation: i sky = i out1 ? v out1 + i out2 ? v out2 + i out3 ? v out3 + i out4 ? v out4 ? ? ? ? ? ? 50 ? v in where i outx is the desired output current from channel x, v outx is the programmed output voltage of channel x, and v in is input voltage. once the sky pin output current requirement is deter - mined, the inductor value can be calculated based on the maximum tolerable inductor current ripple from the following equation: l = v in ? dc5 2 ? f sw ? 0.3 ? 1 ? 0.25 ? dc5 ( ) ? i sky ? ? ? ? where f sw is the programmed switching frequency and dc5 is the boost regulator duty cycle, given by: dc5 = 5v/(v in + 5v). for a 1mhz application, with v in = 12v, v out1 = 5v, v out2 = 3.3v, v out3 = 2.5v, v out4 = 1.8v, and all channels sup - plying 1a of output current, the required sky pin current is 47ma and the inductor value is 6h. soft-start/tracking the run/ss pin can be used to soft-start the correspond- ing channel, reducing the maximum input current during start-up. the run/ss pin is pulled up through a 1a current source to about 2.1v. a capacitor can be tied to the pin to create a voltage ramp at this pin. the buck regulator will not switch while the run/ss pin voltage is less than 0.1v. as the run/ss pin voltage increases above 0.1v, the chan - nel will begin switching and the fb pin voltage will track the run/ss pin voltage (offset by 0.1v), until the run/ss pin voltage is greater than 0.8v + 0.1v. at this point the output voltage will be at 100% of its programmed value and the fb pin voltage will cease to track the run/ss pin voltage and remain at 0.8v (the run/ss pin will continue ramping up to about 2.1v with no effect on the output voltage). the ramp rate can be tailored so that the peak start up current can be reduced to the current that is required to regulate the output, with little overshoot. figure 4 shows the start-up waveforms with and without a soft-start capacitor (c ss ) on the run/ss pin. figure 4a. inductor current waveform during start-up without a soft-start capacitor figure 4b. inductor current waveform during start-up with a 1nf soft-start capacitor (c ss ) 100s/div 3504 f04a i l 0.5a/div v out 2v/div 100s/div 3504 f04b i l 0.5a/div v out 2v/div
lt3504 13 3504f figure 5. circuit to prevent switching when v in < 10v, with 700mv of hysteresis r2 20.5k r1 133k gnd lt3504 en/uvlo v in v in 3504 f05 not switching switching v in, falling = 10v v in (v)v in (v) 9 10 11 12 v in, rising = 11v applica t ions in f or m a t ion undervoltage lockout the lt3504 prevents switching when the input voltage decreases below 3v. alternatively, the en/uvlo pin can be used to program an undervoltage lockout at input voltages exceeding 3v by tapping a resistor divider from v in to en/ uvlo as shown in figure 5. the rising threshold on the en/uvlo pin is 1.44v. the falling threshold on the en/uvlo pin is 1.33v. when en/ uvlo is rising and less than 1.44v then the en/uvlo pin sinks 1.3a of current. this 1.3a current can be used to program additional hysteresis on the en/uvlo pin. for the circuit in figure 5, r1 can be determined from: r1 = v in,hysteresis ? 0.11 1.33 v in,falling ( ) 1.3a where v in,hysteresis is the desired amount of hysteresis on the input voltage and v in,falling is the desired input voltage threshold at which the part will shut down. notice that for a given falling threshold (v in,falling ), the amount of hysteresis (v in,hysteresis ) must be at least: v in, hysteresis > 0.11 1.33 ? v in,falling ( ) for a falling threshold of 10v, the minimum hysteresis is 0.827v. for a falling threshold of 30v, the minimum hysteresis is 2.48v. r2 can be calculated once r1 is known: r2 = r1 ? 1.33 v in, falling ? 1.33 the circuit shown in figure 5 will start when the input voltage rises above 11v and will shutdown when the input voltage falls below 10v. inductor selection and maximum output current a good first choice for the inductor value is: l = 2 ? (v out + v d )/f sw where v d is the voltage drop of the catch diode (~0.4v), l is in h and f sw is in mhz. with this value there will be no subharmonic oscillation for applications with 50% or greater duty cycle. the inductors rms current rating must be greater than your maximum load current and its saturation current should be about 30% higher. for robust operation in fault conditions, the saturation current should be above 2a. to keep efficiency high, the series resistance (dcr) should be less than 0.1 . table 2 lists several vendors and types that are suitable. of course, such a simple design guide will not always result in the optimum inductor for your application. a larger value provides a higher maximum load current and reduces output voltage ripple at the expense of slower transient response. if your load is lower than 1a, then you can decrease the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. low inductance may result in discontinu - ous mode operation, which is okay, but further reduces maximum load current. for details on maximum output current and discontinuous mode operation, see linear technology application note 44.
lt3504 14 3504f applica t ions in f or m a t ion catch diode use a 1a schottky diode. the diode must have a reverse voltage rating equal to or greater than the maximum input voltage. the on semiconductor mbrm140 is a good choice; it is rated for 1a continuous forward current and a maximum reverse voltage of 40v. input capacitor the input of the lt3504 circuit must be bypassed with a x7r or x5r type ceramic capacitor. y5v types have poor performance over temperature and amplified voltage and should not be used. there are four v in pins. each v in pin should be bypassed to the nearest ground pin. however it is not necessary to use a dedicated capaci - tor for each v in pin. pins 9 and 11 may be tied together on the board layout so that both pins can share a single bypass capacitor. since the channels running on pins 9 and 11 are 180 degrees out-of-phase, it is not necessary to double the capacitor value either. similarly, pins 26 and 28 may be tied together on the board layout to save a bypass capacitor. for switching frequencies greater than 750khz, a 1f capacitor or higher value ceramic capacitor should be used to bypass each group of two v in pins. for switching frequencies less than 750khz, a 2.2f or higher value ceramic capacitor should be used to bypass each group of two v in pins. the ceramic bypass capacitors should be located as close to the v in pins as possible. see the sample layout shown in the pcb layout section. all four v in pins should be tied together on the board and bypassing with a low performance electrolytic capacitor is recommended especially if the input power source has high impedance, or there is significant inductance due to long wires or cables. step-down regulators draw current from the input sup- ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3504 and to force this very high frequency switching current into a tight local loop, minimizing emi. to accomplish this task, the input bypass capacitor must be placed close to the lt3504 and the catch diode; see the pcb layout section. a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3504. a ceramic input capacitor combined with trace or cable inductance forms a high quality (underdamped) tank circuit. if the lt3504 circuit is plugged into a live supply, the input voltage can ring to table 2. inductor vendors vendor url part series inductance (h) size (mm) sumida www.sumida.com cdrh4d28 cdrh5d28 cdrh5d28 1.2 to 4.7 2.5 to 10 2.5 to 33 4.5 4.5 5.5 5.5 8.3 8.3 toko www.toko.com a916cy d585lc 2 to 12 1.1 to 39 6.3 6.2 8.1 8 wrth elektronik www.we-online.com we-tpc(m) we-pd2(m) we-pd(s) 1 to 10 2.2 to 22 1 to 27 4.8 4.8 5.2 5.8 7.3 7.3 table 3. capacitor vendors vendor phone url part series comments panasonic (714) 373-7366 www.panasonic.com ceramic, polymer, tantalum eef series kemet (864) 963-6300 www.kemet.com ceramic, tantalum t494, t495 sanyo (408) 749-9714 www.sanyovideo.com ceramic, polymer, tantalum poscap murata (404) 436-1300 www.murata.com ceramic avx www.avxcorp.com ceramic, tantalum tps series taiyo yuden (864) 963-6300 www.taiyo-yuden.com ceramic
lt3504 15 3504f a pplica t ions i n f or m a t ion twice its nominal value, possibly exceeding the lt3504s voltage rating. this situation can be easily avoided by add- ing an electrolytic capacitor in parallel with the ceramic input capacitors. see application note 88. output capacitor the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the lt3504 to produce the dc output. in this role it deter - mines the output ripple so low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the lt3504s control loop. ceramic capacitors have very low equivalent series re - sistance (esr) and provide the best ripple performance. a good value is: c out = 33/(v out ? f sw ) where c out is in f and f sw is in mhz. use x5r or x7r types and keep in mind that a ceramic capacitor biased with v out will have less than its nominal capacitance. this choice will provide low output ripple and good transient response. transient performance can be improved with a high value capacitor, if the compensation network is also adjusted to maintain the loop bandwidth. a lower value of output capacitor can be used, but transient performance will suffer. high performance electrolytic capacitors can be used for the output capacitor. low esr is important, so choose one that is intended for use in switching regulators. the esr should be specified by the supplier and should be 0.1 or less. such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance, because the capacitor must be large to achieve low esr. table 3 lists several capacitor vendors. figure 6 shows the transient response of the lt3504 with several output capacitor choices. the output is 3.3v. the load current is stepped from 500ma to 1a and back to 500ma and the oscilloscope traces show the output volt- age. the upper photo shows the recommended value. the second photo shows the improved response (less voltage drop) resulting from a larger output capacitor and a larger phase lead capacitor. the last photo shows the response to a high performance electrolytic capacitor. transient per - formance is improved due to the large output capacitance. shorted and reversed input protection if the inductor is chosen so that it wont saturate exces- sively, an lt3504 buck regulator will tolerate a shorted output. there is another situation to consider in systems where the output will be held high when the input to the lt3504 is absent. this may occur in battery charging ap - plications or in battery backup systems where a battery or some other supply is diode or-ed with the lt3504s output. if the v in pin is allowed to float and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the lt3504s internal circuitry will pull its quiescent current through its sw pin. this is fine if your system can tolerate a few ma in this state. if you ground the en/uvlo pin, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3504 can pull large currents from the output through the sw pin and the v in pin. figure 7 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input.
lt3504 16 3504f figure 6. transient load response of the lt3504 with different output capacitors as the load current is stepped from 500ma to 1a. v in = 12v, v out = 3.3v, l = 10h, r t = 18.2k 10f 31.6k 10k i out 1a/div v out 20mv/div i out 1a/div v out 20mv/div 20s/div 20s/div i out 1a/div v out 20mv/div 20s/div v out 3504 f06a 3504 f06b 3504 f06c v out 31.6k 10k 10f 2 100pf 31.6k 10k v out + 22f fb lt3504 fb lt3504 fb lt3504 applica t ions in f or m a t ion figure 7. diode d4 prevents a shorted input from discharging a backup battery tied to the output; it also protects the circuit from a reversed input. the lt3504 runs only when the input is present 3504 f07 d4 v in v out backup gnd lt3504 sw1 da1 fb1 en/uvlo sky sw5 v in v in run/ss1 rt/sync
lt3504 17 3504f applica t ions in f or m a t ion pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 8 shows the recommended component placement with trace, ground plane, and via locations. note that large, switched currents flow in the lt3504s v in , sw and da pins, the catch diodes (d1, d2, d3, d4) and the input capacitors (c5, c6). the loop formed by these components should be as small as possible and tied to system ground in only one place. these components, along with the inductors (l1, l2, l3, l4, l5) and output capacitors (c1, c2, c3, c4, c7), should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location (ideally at the ground terminal of the output capacitors). ground pins (pins 10, 27) are provided near the v in pins so that the v in pins can be bypassed to these ground pins. the sw nodes should be kept as small as possible and kept far away from the rt/sync and fb nodes. keep the rt/ sync node and fb nodes small so that the ground pin and ground traces will shield them from the sw nodes. if the user plans on using a sync signal to set the oscillator frequency then the rt/sync node should be kept away from the fb nodes. include vias near the exposed pad of the lt3504 to help transfer heat from the lt3504 to the ground plane. keep the sw5 pad/trace as far away from the fb pads as possible. high temperature considerations the die temperature of the lt3504 must be lower than the maximum rating of 125c. this is generally not a concern unless the ambient temperature is above 85c. for higher temperatures, extra care should be taken in the layout of the circuit to ensure good heat sinking of the lt3504. the maximum load current should be derated as the ambient temperature approaches 125c. programming the lt3504 to a lower switching frequency will improve efficiency and reduce the dependence of efficiency on input voltage. the die temperature is calculated by multiplying the lt3504 power dissipation by the thermal resistance from junc- tion to ambient. power dissipation within the lt3504 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the catch diode losses. thermal resistance depends on the layout of the circuit board, but 43c/w is typical for the mse package. thermal shutdown will turn off the buck regulators and the boost regulator when the die temperature exceeds 175c, but this is not a warrant to allow operation at die temperatures exceeding 125c. outputs greater than 9v for outputs greater than 9v, add a 1k resistor in series with a 1nf capacitor across the inductor to damp the discon - tinuous ringing of the sw node, preventing unintended sw current. an application with a 15v output (back page) shows the location of this damping network. other linear technology publications application notes 19, 35, 44 contain more detailed descrip- tions and design information for step-down regulators and other switching regulators. design note 318 shows how to generate a bipolar output supply using a step-down regulator.
lt3504 18 3504f a pplica t ions i n f or m a t ion figure 8 via to local ground plane outline of local ground plane via to vin 3504 f08 + l5 d3 d1 d2 d4 c7 sw5 vin vin gnd gnd gnd gnd rt/sync gnd gnd fb2 fb3 fb1 fb4 sky sw2 sw3 sw4 c4 sw1 out2 out3 out4 out1 gnd c3 gnd c1 c2 c8 l3 l2 l1 l4 c5 c6 run/ss4 run/ss1 run/ss2 run/ss3 en/uvlo r9 gnd pg r2 r5 r3 r6 r1 r7 r4 r8
lt3504 19 3504f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05
lt3504 20 3504f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0712 ? printed in usa r ela t e d p ar t s typical a pplica t ion 40v quad output application at 500khz 3504 ta02 sw4 da4 fb4 sw3 da3 fb3 sw2 da2 fb2 sw1 da1 fb1 sky sw5 en/uvlo v in v in v in v in run/ss1 run/ss2 run/ss3 run/ss4 rt/sync 1.2v/200ma 4.7h 16.9k 33.2k 100f 7v/200ma 10h 15h 39.2k 4.99k 1.02k 10f 1f v in 15.4v to 40v 50nf 2.2f 15v/200ma 10h 1nf 45.3k 2.55k 4.7f 3.3v/200ma 4.7h 43.2k 13.7k 43.2k 22f gnd lt3504 2.2f part description comments lt3507/ lt3507a 36v 2.5mhz, triple [2.4a + 1.5a + 1.5a (i out )] with ldo controller high efficiency step-down dc/dc converter v in(min) = 4v, v in(max) = 36v, v out(min) = 0.8v, i q = 7ma, i sd = 1a, 5mm x 7mm qfn-38 package LT8610 42v 2.2mhz, synchronous, low i q = 2.5a, step-down dc/dc converter v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = 1a, msop-16e package lt3988 60v with transient protection to 80v, 2.5mhz, dual 1a high efficiency step-down dc/dc converter v in(min) = 4.0v, v in(max) = 60v, v out(min) = 0.75v, i q = 2ma, i sd = 1a, msop-16e package lt3509 36v with transient protection to 60v, dual 0.70(i out ), 2.2mhz, high efficiency step-down dc/dc converter v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 1.9ma, i sd = 1a, 3mm 4mm dfn-14, msop-16e packages lt3500 36v, 40v max , 2a, 2.5mhz high efficiency step-down dc/dc converter and ldo controller v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 2.5ma, i sd <10a, 3mm 3mm dfn-10 package lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 3mhz, high efficiency step-down dc/dc converter v in(min) = 3.7v, v in(max) = 37v, v out(min) = 0.8v, i q = 4.6ma, i sd = 1a, 4mm 4mm qfn-24, tssop-16e packages lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode ? operation v in(min) = 3.6v, v in(max) = 58v, transient to 80v, v out(min) = 0.8v, i q = 85a, i sd <1a, 3mm 4mm dfn-16 and msop-16e packages lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in(min) = 3.6v, v in(max) = 38v, v out(min) = 0.78v, i q = 70a, i sd <1a, 3mm 3mm dfn-10, msop-10e packages lt3689 36v, 60v transient protection, 800ma, 2.2mhz high efficiency micropower step-down dc/dc converter with por reset and watchdog timer v in(min) = 3.6v, v in(max) = 36v, transient to 60v, v out(min) = 0.8v, i q = 75a, i sd <1a. 3mm 3mm qfn-16 package lt3970 40v, 350ma, 2mhz high efficiency micropower step-down dc/dc converter v in(min) = 4v, v in(max) = 40v, transient to 60v, v out(min) = 1.21v, i q = 2a, i sd <1a, 3mm 2mm dfn-10 and msop-10 packages lt3682 36v, 60vmax, 1a, 2.2mhz high efficiency micropower step-down dc/dc converter v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3mm 3mm dfn-12 package

▲Up To Search▲

Price & Availability of LT8610

	To Download LT8610 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .